1. Field of the Invention
The present invention relates to a circuit of controlling a pulse width, and more particularly to, a circuit for controlling a pulse width of a column address select signal.
2. Discussion of Related Art
A high speed DRAM or DDR has been recently used in a graphic field. Operations of those devices are remarkably affected by a pulse width, especially by a column address select signal.
The DRAM for a graphic operating in various frequency domains of low frequency to high frequency is operated in a wide frequency domain, which occurs many problems. Especially, in case of a column address select signal, each of the signals should have an appropriate pulse width for each operation frequency, to be stable for read and write operations of a DRAM data. Accordingly, it is important for the column address select signal to have an appropriate pulse width according to the operation frequency. In the conventional technique, the pulse width of the column address select signal is preset a predetermined value or controlled by an external clock.
A method of setting the pulse width of the column address select signal as a predetermined value is to generate a constant pulse width regardless of tCK, namely a frequency. In this case, although the frequency is risen, which means the tCK is decreased, the column address select signal has a constant pulse width. As a result, during read and write operations of the DRAM, a period activating a local input/output line for transferring an output signal of a bitline sense amplifier to an input/output sense amplifier is wider, but a precharge period is narrower. Accordingly, if a read or a write operation command is inputted sequentially in a disprecharge state, other data (can be error) are available to be read or written, degrading reliability of the data.
In addition, in a method for controlling the column address select signal by the external clock, the tCK is decreased in a high frequency, which results to narrow the activation period for the local input/output line. As a result, when the read and write operations are performed, especially the read operations is performed, ΔV of the local input/output line is reduced, thereby disadvantageous to use a wrong data in the input/output sense amplifier.